首页> 外文会议>International Symposium for Testing and Failure Analysis(ISTFA 2004); 20051106-10; San Jose,CA(US) >Stacked-Die Failure Mechanisms for an Octal, Current Input 20-Bit Analog-to-Digital Converter
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Stacked-Die Failure Mechanisms for an Octal, Current Input 20-Bit Analog-to-Digital Converter

机译:八通道,电流输入20位模数转换器的叠层模故障机制

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Stacked-die packaging was used to make an octal 20-bit analog-to-digital (A/D) converter by stacking two quad A/D converter die in a single 48-lead QFN (quad flat-pack, no leads) package. Reliability testing for product qualification initially failed only (biased) HAST test. Two failure mechanisms were identified. The first mechanism was silver ion migration at sensitive analog inputs due to high conductive die-attach fillets on the bottom die. The second mechanism was ILD delamination and passivation layer cracking due to spacer-attach stress on the surface of the bottom die. Electrical failure analysis was aided by a self test mode designed into the quad A/D converter. Package opening and other standard failure analysis techniques required some modification to accommodate the stacked-die package. This work points to critical stacked-die assembly steps, including conductive die-attach and nonconductive spacer-attach application, where effects of moisture, bias, and thermal stress must all be considered.
机译:堆叠管芯封装用于通过将两个四方A / D转换器管芯堆叠在单个48引线QFN(四方扁平封装,无引线)封装中来制造八位20位模数(A / D)转换器。 。产品合格性的可靠性测试最初仅(偏向)HAST测试失败。确定了两种故障机制。第一种机制是由于底部芯片上的高导电芯片连接圆角,银离子在敏感的模拟输入处迁移。第二种机制是由于下模表面上的垫片附着应力造成的ILD分层和钝化层破裂。电气故障分析是通过在四通道A / D转换器中设计的自测模式进行的。封装打开和其他标准的故障分析技术需要进行一些修改,以适应堆叠式芯片封装。这项工作指出了关键的堆叠管芯组装步骤,包括导电管芯附着和非导电间隔片附着应用,在这些步骤中,必须充分考虑水分,偏压和热应力的影响。

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