FPGA Implementation for the Lifting-based 5/3 Inverse Discrete Wavelet Transform

摘要

Discrete Wavelet Transform(DWT) has become very popular as the basis of many recent image processing and compression techniques. In the new image compression standard JPEG2000, 5/3 Forward Discrete Wavelet Transform(FDWT) and Inverse Discrete Wavelet Transform(IDWT) was adopted and can be used for lossy/lossless image compression. We presented a novel hardware structure for lifting-based 5/3 IDWT, using pipeline technique to improve processing efficiency. We implemented the design in HDL and validated it on an FPGA.