Adiabatic 3.7nJ 72-Point Prime-Factor FFT Processor Core

摘要

This paper describes a 3.7nJ custom adia-batic 72-point FFT processor core for audio applications, implemented in a standard 0.25μm CMOS process. A number of optimizations was applied across the design hierarchy to facilitate energy recovery, simplify computation and allow low voltage circuit operation. The major arithmetic building block used is a novel, ROM-less distributed arithmetic architecture (DAA), consisting of high fan-in, adia-batic counter logic gates. The low circuit complexity of this architecture has enabled a simple VLSI implementation of the prime-factor FFT algorithm, featuring a high level of parallelism. As a result of the overall optimization, the energy efficiency of the FFT processor powered from a 1V adiabatic power generator, is 4.7 times higher than that of an equivalent conventional CMOS, low-power FFT implementation.