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Verification Condition Generation Via Theorem Proving

机译:通过定理证明生成验证条件

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摘要

We present a method to convert (ⅰ) an operational semantics for a given machine language, and (ⅱ) an off-the-shelf theorem prover, into a high assurance verification condition generator (VCG). Given a program annotated with assertions at cutpoints, we show how to use the theorem prover directly on the operational semantics to generate verification conditions analogous to those produced by a custom-built VCG. Thus no separate VCG is necessary, and the theorem prover can be employed both to generate and to discharge the verification conditions. The method handles both partial and total correctness. It is also compositional in that the correctness of a subroutine needs to be proved once, rather than at each call site. The method has been used to verify several machine-level programs using the ACL2 theorem prover.
机译:我们提出一种将给定机器语言的(ⅰ)操作语义和(ⅱ)现成的定理证明者转换为高保证验证条件生成器(VCG)的方法。给定一个在断点处标注断言的程序,我们将展示如何在操作语义上直接使用定理证明者来生成类似于定制VCG产生的验证条件。因此,不需要单独的VCG,并且可以使用定理证明者来生成和释放验证条件。该方法处理部分和全部正确性。这也是一个组成部分,因为子例程的正确性需要被证明一次,而不是在每个调用位置。该方法已用于使用ACL2定理证明器验证多个机器级程序。

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