Overcoming the Limitations of the Traditional Loop Parallelization

摘要

Previous research has shown existence of a huge potential of the coarse-grain parallelism in programs. This parallelism is however not always easy to exploit. Especially, when applying today's parallelizing compilers to typical applications from the "embedded" domain. This is mainly due to the deficiencies of the static data dependency analysis they relay on. This paper investigates the potentials of the loops parallelization techniques using dynamic loop analysis techniques. For a set of "embedded" behcmarks (including an MEPG-2 encoder) arpprox4 times more loops culd be parallelized. in comparison with a state-of-the-art comiler (SUIF (1)), leading to average speedups of 2.85 (on a 4 processor system). Dynamic analysis is however not "full-proof"-we intent to use it exclusively in cases when static analysis fails to given any answer, and only if tha user asserts its applicability.