Reconfigurable circuits such as FPGAs become much larger, reaching the 100.000 gates, and are a credible alternative for some computation intensive applications. However, to the accepted, very important progresses must be achieved in the programming methods, since several bottlenecks limit the design process for FPGA. Generating a circuit from an high level specification involves numerous tasks. The goal of the logic synthesis task is to improve the circuit on criteria such as speed or area, and to take technology constraints into account. The aim of our work is to speed up this phase, since it involves important runtime and huge memory requrments, even if heuristics are used.
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