System-Level Power-Performance Trade-Offs in Task Scheduling for Dynamically Reconfigurable Architectures

摘要

Dynamic scheduling for System-on-Chip (SoC) platforms has become an important field of research due to the emerging range of applications with dynamic behavior (e.g. MPEG-4). Dynamically reconfigurable architectures are an interesting solution for this type of applications. However, dynamic scheduling for run-time reconfigurable architectures with power-performance trade-offs has not been addressed in previous research efforts. In this paper, we address this open issue using a system-level approach. Within our approach, we have used clock-gating and frequency-scaling strategies for power consumption minimization, jointly with our proposed architecture and scheduling algorithms. Device reconfiguration is a high-power consumption process. Thus reducing the number of device reconfigurations not only helps to reduce the reconfiguration overhead penalty (minimizing the application execution time), but also helps to reduce the system-level power consumption. Thus, dynamic task scheduling and reconfiguration context scheduling become a critical issue for power-performance trade-offs in embedded systems design. We have designed, manufactured and used in our experiments a dynamically reconfigurable architecture based on a Virtex-II Pro device. A large number of experiments have been carried out on top of this architecture to explore the power-performance tradeoffs in task scheduling for dynamically reconfigurable architectures.