A Unified Compressed Cache Hierarchy With Partial Cache Line Prefetching Used for SMT Processor

摘要

This paper proposes a novel compressed cache hierarchy (UCCH, Unified Compressed Cache Hierarchy) that uses a unified compression algorithm, called Simple Frequent Pattern Compression (S-FPC), in both LI data cache and L2 cache to improve SMT processor performance. With the data locality of LI D-cache and L2 cache hurted by the competition of on-chip cache resources among threads, SMT technology distinctly increase the data bus bandwidth requirements between levels of caches and cache capacity requirements of LI D-cache and L2 cache. Because UCCH can increase the cache capacity of LI data cache and L2 cache without any sacrifice of the LI cache access latency, and the layout of compressed data in LI D-cache enable partial cache prefetching without introducing prefetch buffer or increasing cache pollution and memory traffic, UCCH is beneficial to improve SMT processor performance. The experiments showed that our unified compressed cache hierarchy can decrease LI D-cache miss rate 17.1%, decrease L1-L2 bus occupancy rate 15.3%, decrease main memory traffic bandwidth demand 49.3%, and improve instruction throughput 4.5% relative to tradition cache configure in SMT processor.