Low Energy I-Cache for Embedded Processors

摘要

Energy consumption plays a crucial role in the design of embedded processors especially for portable devices that depends of batteries for power. Since memory access consumes a significant portion of the energy of a processor, the design of fast low-energy caches has become a very important aspect of modern processor design. In this paper, we present a novel cache architecture for reduced energy instruction caches. Our proposed cache architecture consists of the L1 cache, multiple line buffers, and a prediction and placement mechanism to predict which line buffer, or L1 cache to access next. We used simulation to evaluate our proposed architecture and compare it with the HotSpot cache, Filter cache, and single line buffer cache. Simulation results show that our approach is slightly faster than the above mentioned caches, and it consumes considerably less energy than any of these caches.