Transaction Level Modeling for Hardware Architecture Exploration with IEEE 802.1 In Receiver Example

摘要

This paper gives an overview of a transaction level modeling (TLM) design flow for the hardware architecture exploration with SystemC. TLM is widely used for Hardware-Software codesign, since the objective of TLM is the system exploration in the early stage of the design with fast but accurate simulation with abstracted transaction between modules in system. In this paper, we exploit the concept of TLM for the hardware architecture exploration. SystemC description methodology for TLM is described and the hardware architecture exploration of IEEE 802.1 In PHY receiver is presented.