Designing Leading Zeros Anticipatory Logic based on Production Rules

摘要

This paper presents a more efficient leading-zeros anticipatory (LZA) logic for high-performance floatingpoint computation. The leading zeros anticipation is a critical process to anticipate the number of leading zeros of the addition result in parallel with floating-point addition. However, a potential error by one bit exists in the previous anticipation schemes. In those schemes, some logic was proposed to correct the error after the addition and its leading zeros anticipation, but extra latency was introduced and lience the hardware complexity increased. In our approach, based on a set of production rules, the leading zeros are anticipate exactly, and no correction step is necessary any more. The production rules are very simple and easy to realize. The latency and logic complexity of the proposed production rules are discussed. Both speed and area advantages are presented.