Design Theory and Library Development of Vertical Dual Carrier Field Effect Transistor ASIC and SOC on SiO_2 and Insulating GaAs Substrate with Effective Channel Length of 5-30nm

摘要

Design theory and library development of Vertical Dual Carrier Field Effect Transistor (VDCFET) ASIC and SOC on SiO_2 and insulating GaAS substrate are presented for VDCFET with effective channel length of 5-30 nm. These ASIC and SOC can be designed for different materials. For different applications, these VDCFET have different equivalent circuits, thus different library development are described. It is to be emphasized that these VDCFET ASIC and SOC, with effective channel length of 5-30 nnm, can be fabricated with lithographic equipment for linewidths of 90 nm, 130 nm, 180 nm or more. The design theory of "Vertical Dual Carrier Field Effect Transistor" (VDCFET) is presented in this paper. It shall be illustrated that effective channel lengths as short as 5-30nm can be designed by proper choice of device dimensions, doping and device terminal voltages. The fabrication process of these VDCFET is compatible with that of CMOS, HBT and BiCMOS, using lithographic equipment for linewidths of 90nm, 130nm or 180nm. The number of transistors which can be integrated in each ASIC or SOC depends upon the lithographic equipment to be used.