【24h】

Ready Simulation for Concurrency: It's Logical!

机译:准备好并发仿真:这是合乎逻辑的!

获取原文
获取原文并翻译 | 示例

摘要

This paper provides new insight into the connection between the trace-based lower part of van Glabbeek's linear-time, branchingtime spectrum and its simulation-based upper part. We establish that ready simulation is fully abstract with respect to failures inclusion, when adding the conjunction operator that was proposed by the authors in [TCS 373(1-2): 19-40] to the standard setting of labelled transition systems with (CSP-style) parallel composition. More precisely, we actually prove a stronger result by considering a coarser relation than failures inclusion, namely a preorder that relates processes with respect to inconsistencies that may arise under conjunctive composition. Ready simulation is also shown to satisfy standard logic properties and thus commends itself for studying mixed operational and logic languages.
机译:本文提供了对Van Glabbeek的线性时间,分支时间谱的基于迹线的下部与其基于仿真的上部之间的联系的新见解。我们确定,当将作者在[TCS 373(1-2):19-40]中提出的联合运算符添加到带有(CSP)的标记过渡系统的标准设置中时,就故障包含而言,现成的仿真是完全抽象的样式)并行组成。更确切地说,我们实际上通过考虑比故障包含更粗糙的关系证明了更强的结果,该关系是将过程与在组合构成下可能出现的不一致相关联的预排序。准备就绪的仿真也显示出满足标准逻辑属性的要求,因此值得称赞其用于研究混合操作语言和逻辑语言。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号