Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs

摘要

In the emerging era of large scale SoCs comprised from complex IPs, typically designed for AI and Automotive applications, it is essential to embrace an innovative approach to overcome DFT challenges. One of these challenges is to provide a fast time to market solution. This solution must be generic, scalable, robust and Functional Safety (FuSa) aware. To accomplish this challenge, a generic Virtual Memory Wrapper (VMW) and a Virtual Memory Container (VMC) are introduced. These structures provide highly parametrized and scalable design, accompanied by a push-button memory BIST insertion flow. This innovative approach allows full decoupling between Functional & Test design aspects of a complex SoC.