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A Framework for Design of Self-Repairing Digital Systems

机译:自修复数字系统设计框架

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摘要

This paper introduces a scalable framework for the design of self-testable, self-correcting, and self-repairing digital systems. Modular redundancy and re-programmability are used to accomplish generic self-test and to enable self-repair. Bit error rates (BER) are measured throughout the design to distinguish between transient errors and errors due to semi- or permanent-logic faults. Tri-modular redundancy (TMR) is used for error correction and fault-isolation with a fourth module available for automated repair. Modular reconfiguration (repair) occurs automatically, so that the system continues to operate error-free even during partial dynamic reconfiguration (in FPGAs). The state of a repaired module is re-synchronized with the running system within one cycle after the damaged module is replaced. The framework is capable of simultaneous repair of multiple faults, while ensuring error-free operation. A case study evaluates the reliability improvement of an FPGA-based neural network image classification application.
机译:本文介绍了一种可扩展的框架,用于设计自测,自校正和自修复的数字系统。模块化冗余和可重编程性用于完成通用的自检并实现自我修复。在整个设计中都对误码率(BER)进行了测量,以区分瞬态错误和半逻辑或永久性逻辑错误导致的错误。三模冗余(TMR)用于纠错和故障隔离,第四个模块可用于自动修复。模块化重新配置(修复)自动进行,因此即使在部分动态重新配置期间(在FPGA中),系统也可以继续无错误地运行。在更换损坏的模块后的一个周期内,已修复模块的状态将与正在运行的系统重新同步。该框架能够同时修复多个故障,同时确保无错误运行。案例研究评估了基于FPGA的神经网络图像分类应用程序的可靠性改进。

著录项

  • 来源
    《International Test Conference》|2019年|1-10|共10页
  • 会议地点 Washington(US)
  • 作者

    Jingchi Yang; David C. Keezer;

  • 作者单位

    School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta USA;

  • 会议组织
  • 原文格式 PDF
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