Time-Slicing Soft Error Resilience in Microprocessors for Reliable and Energy-Efficient Execution

摘要

Resilience to soft errors is essential for ensuring the robustness of a computing system. In this paper, we present a new soft error resilience approach called TSSER (time-sliced soft error resilience), which enables resilience features for instructions that are most likely to cause errors only to minimize system-level energy costs while achieving high levels of resilience. Our TSSER idea (1) takes advantage of the observation that protecting a fraction of the instructions in an application already achieves most of the resilience benefits, (2) utilizes circuit-level features that allow resilience mode to be turned on/off, and (3) bridges the gap between application knowledge and circuit features by devising novel ISA and microarchitectural techniques to achieve optimized tradeoffs. Our results obtained from RTL implementation and detailed simulation show that, for various applications from the SPEC and PARSEC benchmark suites, TSSER achieves 65X reduction in SDC rate (a common metric to measure soft error resilience) while imposing 16.8% (11.3%) processor-level energy cost for in-order (out-of-order) processors. This is a significant improvement compared to existing techniques that impose 32% - 81% (18% -83 %) energy overhead. Our technique also enables flexible tradeoffs between SDC rate and system costs.