Digital Pulse-Width Modulator with Asynchronous Change of Compare Register Value and Short Delay Time*

摘要

This paper presents an analysis of signal delay time in implementation of digital pulse-width modulators (DPWM). The paper demonstrates that the most essential component of delay time in a digital modulator is the time required for implementation of DPWM, and that it is almost always understood that the DPWM is a type 1 PWM. It is shown that the maximum delay time in such approach to DPWM implementation within the range cannot be less than one PWM conversion period. A new approach to DPWM implementation is proposed, suggesting an increase of the number of signal measurements within a PWM period and an asynchronous change of the compare register value in the digital comparator. Signal delay in the proposed DPWM is reduced N times, where N is the number of signal measurements within a PWM period. The proposed approach essentially results in implementation of a DPWM as a type 2 PWM.