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Forming Low-Resistivity Electrodes of Thin Film Transistors with Selective Electroless Plating Process

机译:通过选择性化学镀工艺形成薄膜晶体管的低电阻电极

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The silver gate and source/drain electrodes for ana-Si thin film transistor were fabricated by theselective electroless plating (SELP) process. Relevantphysical properties including taper angle, uniformityand resistivity are investigated. The Ag layer wasabout 150nm to 250nm thick, the resistivity less than3x10-6 Ohm-cm and the taper angle 45 - 60 and thenonuniformity less than 10% on G2 substrates. Thetransfer characteristics with the Ag gate, andsource/drain electrodes respectively possessed goodfield effect mobility similar to conventionallyfabricated a-Si TFTs. This process provided lowresistivity, low cost and ease of processing.
机译:通过选择性化学镀(SELP)工艺制造了用于ana-Si薄膜晶体管的银栅电极和源/漏电极。研究了相关的物理性质,包括锥角,均匀性和电阻率。在G2衬底上,Ag层的厚度约为150nm至250nm,电阻率小于3x10-6 Ohm-cm,锥角为45-60,非均匀性小于10%。 Ag栅电极和源/漏电极的转移特性分别具有与常规制造的a-Si TFT相似的良好场效应迁移率。该工艺提供了低电阻率,低成本和易于加工。

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