Delay estimation, chip-power analyses and comparison of single-level and multi-level recursive vedic algorithm with conventional algorithms for digital multiplier

摘要

With advent of digital circuits and systems, multipliers have become important functional blocks in digital and mixed-mode operations, in fast processors and micro-controllers design for applications in signal processing, data converters etc. Unfortunately however, very few original algorithms have been reported till date for speed-power optimization in multiplier design. As such processors and/ or digital systems having multiplier blocks continue to use the age-old time-tested Booth algorithm combined with its modifications proposed by Wallace and Dadda. Hence it became imperative to explore new fast multiplier algorithms and optimize their architectures in order to minimize area, complexity by reducing multiplication steps, to maximize speed, yet limiting power-dissipation. This paper re-introduces the Vedic algorithm named Karatsuba-algorithm that was invented for decimal-multiplication and then proposes a novel technique to make it a multi-level, recursive algorithm to further maximize the speed advantage in binary multiplication. A performance comparison of existing array algorithms like Booth Structure and Wallace Tree with the proposed Karatsuba technique and its recursive multi-tiring proposed by these authors, reveal that the proposed modification on Karatsuba algorithm results in most optimized performance on speed-power.