Group of Electronic Design, Faculty of Science, Universidad de Zaragoza, C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;
Group of Electronic Design, Faculty of Science, Universidad de Zaragoza, C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;
Group of Electronic Design, Faculty of Science, Universidad de Zaragoza, C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;
Group of Electronic Design, Faculty of Science, Universidad de Zaragoza, C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;
Group of Electronic Design, Faculty of Science, Universidad de Zaragoza, C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;
High-speed communications; SI-POF; continuous-time equalization; duobinary modulation;
机译:3.125 Gbit / s CMOS收发器,可在50-m SI-POF通道上进行双二进制调制
机译:具有成本效益的1.25 Gb / s CMOS接收器,用于50 m大核SI-POF链路
机译:84 Gbit / s SiGe BiCMOS双二进制串行数据链路,包括串行器/解串器(SERDES)和5抽头FFE
机译:CMOS前端用于超过50米SI-POF链路的调整数据
机译:用于千兆位串行数据链路的CMOS集成锁相环设计。
机译:用于高速ATLAS Muon漂移管检测器的28 nm批量CMOS模拟前端
机译:CMOS 0.18μm技术的1.2 Gb / s数据传输单元,用于ALICE内部跟踪系统前端ASIC