A decision feedback equalizer with a frequency offset compensatingcircuit for digital cellular radio

摘要

The performance of a decision feedback equalizer (DFE) with anfrequency offset compensating circuit for the North American digitalncellular system (NADC) is presented. The carrier frequency offset at thenequalizer's output deteriorates performance of the DFF. Using the unitnupper triangular matrix diagonal matrix decomposition type recursivenleast squares algorithm as an adaptive algorithm, a frequency offsetncompensating circuit, which is composed of a phase locked loop (PLL), isnused. Simultaneous control of the DFE and PLL is effectively utilized tonimprove the performance. A BER below 3% for all delays up to one symbolnperiod can be achieved when the averagenE_b/N₀ is 20 dB, the fadingnfrequency is 80 Hz and the carrier frequency offset is 200 Hz in thensimulation results. The authors assume the two rays equal powernmultipath Rayleigh fading model, the same as the NADC specifications.nThe influence of quantization in the calculation is described. Thenmantissa-field occupies 8 bits and the exponent-field occupies 6 bits