Hierarchical Extraction of Critical Area for Shorts in Very Large ICs

摘要

This paper describes an algorithm for efficiently extracting critical area in large VLSI circuits. The algorithm, implemented to handle shorts between electrical nets, takes advantage of the available hierarchy in the layout description in order to speed-up computation and minimize memory usage. The developed software - CREST - was tested for a spectrum of actual IC designs and was found very efficient as compared to existing techniques.