Implementation of operand decomposition in signed logarithmic multipliers

摘要

Digital signal processing applications mainly make use of multipliers which determine the overall performance of the system. The existing multiplier architectures are very complex and consume more time. Mitchell's Algorithm (MA) is a modest approach to compute the product using simple logarithmic operations and thus, achieving higher speed. Operand Decomposition (OD) reduces the switching activity and hence, achieves a better accuracy in fractional part calculation of logarithm. Divided Approximation (DA) and Table of Correction Values (TCV) are error correction approaches for MA which tries to follow the logarithmic curve more closely. Signed logarithmic multiplication using operand decomposition is proposed. The existing MA, DA and the proposed signed MA-OD, OD-DA, TCV are coded using Verilog HDL, simulated using ModelSim and synthesized using Xilinx XST. The simulated results are compared with respect to mean absolute error. The comparison results show that OD-DA and TCV significantly improve the accuracy of MA and found to decrease the mean absolute error of MA from around 5.36% to 1.7% and 1.33% respectively.