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Adaptive Cache Bypassing for Inclusive Last Level Caches

机译:包含性末级缓存的自适应缓存绕过

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Cache hierarchy designs, including bypassing, replacement, and the inclusion property, have significant performance impact. Recent works on high performance caches have shown that cache bypassing is an effective technique to enhance the last level cache (LLC) performance. However, commonly used inclusive cache hierarchy cannot benefit from this technique because bypassing inherently breaks the inclusion property. This paper presents a solution to enabling cache bypassing for inclusive caches. We introduce a bypass buffer to an LLC. Bypassed cache lines skip the LLC while their tags are stored in this bypass buffer. When a tag is evicted from the bypass buffer, it invalidates the corresponding cache lines in upper level caches to ensure the inclusion property. Our key insight is that the lifetime of a bypassed line, assuming a well-designed bypassing algorithm, should be short in upper level caches and is most likely dead when its tag is evicted from the bypass buffer. Therefore, a small bypass buffer is sufficient to maintain the inclusion property and to reap most performance benefits of bypassing. Furthermore, the bypass buffer facilitates bypassing algorithms by providing the usage information of bypassed lines. We show that a top performing cache bypassing algorithm, which is originally designed for non-inclusive caches, performs comparably for inclusive caches equipped with our bypass buffer. The usage information collected from the bypass buffer also significantly reduces the cost of hardware implementation compared to the original design.
机译:高速缓存层次结构设计(包括绕过,替换和包含属性)会对性能产生重大影响。高性能高速缓存的最新工作表明,高速缓存绕过是增强最后一级高速缓存(LLC)性能的有效技术。但是,常用的包含式缓存层次结构无法从此技术中受益,因为绕过会固有地破坏包含性。本文提出了一种为包含性缓存启用缓存绕过的解决方案。我们为LLC引入了旁路缓冲区。旁路高速缓存行将其标签存储在此旁路缓冲区中时跳过LLC。当标签从旁路缓冲区中退出时,它会使上级缓存中的相应缓存行无效,以确保包含属性。我们的主要见解是,假设绕行算法的设计合理,绕行的生命周期在高层缓存中应较短,并且当其标签从绕行缓冲区中逐出时,很可能会死掉。因此,一个小的旁路缓冲器足以维持包含特性并获得旁路的大多数性能优势。此外,旁路缓冲器通过提供旁路线路的使用信息来促进旁路算法。我们展示了性能最高的缓存绕过算法,该算法最初是为非包含式缓存设计的,与配备了旁路缓冲区的包含式缓存相比,性能相当。与原始设计相比,从旁路缓冲区收集的使用信息还大大降低了硬件实现的成本。

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