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Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays

机译:多个哈希匹配单元(MHMU):用于现场可编程门阵列的三元算法可编址内容存储器设计

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As applications and user requirements are constantly evolving, there is a need to provide flexible networks that are able to process packets at high speed. One of the basic functions used for packet processing is matching a key formed by some fields of the incoming packet header against a set of stored rules. This is done for example to determine the next hop of a packet or to apply security checks on a firewall. In many cases, the stored rules have do not care bits as that enables a more flexible and compact representation of the rules. Therefore, the matching can be done in hardware using Ternary Content Addressable Memories (TCAMs). However, TCAMs pose several problems in many implementations. For example, for ASICs they require much more circuit area and power than standard SRAMs. On the other hand, designs based on programmable logic such as Field Programmable Gate Arrays (FPGAs) can only use the blocks provided by the FPGA that do not typically include TCAMs. In this last case, a TCAM can be emulated using the FPGA logic resources but with a large cost. To reduce the cost of implementing TCAMs, a number of algorithmic solutions have been proposed and are known as Algorithmic TCAMs or A-TCAMs. Most of those schemes target either software or ASIC implementations. In this paper we present Multiple Hash Matching Units (MHMU) an A-TCAM solution targeted towards FPGA implementations. The proposed scheme exploits the massive parallelism of FPGAs to implement many hash based matching units that use the embedded block RAM memories of the FPGA. The proposed MHMU scheme has been mapped to a Xilinx series 7 FPGA to check its efficiency in terms of resource usage and its scalability. To validate the effectiveness of MHMU, a simple configuration has been tested with Classbench generated sets of rules. The results show that the MHMU is able to consistently accommodate sets with several tens of thousands of rules with large keys.
机译:随着应用和用户需求的不断发展,需要提供一种能够高速处理数据包的灵活网络。用于数据包处理的基本功能之一是将传入数据包报头的某些字段形成的密钥与一组存储的规则进行匹配。这样做是为了确定数据包的下一跳或在防火墙上应用安全检查。在许多情况下,存储的规则不需要关心位,因为这样可以更灵活,更紧凑地表示规则。因此,可以使用三元内容可寻址存储器(TCAM)在硬件中完成匹配。但是,TCAM在许多实现中都存在一些问题。例如,对于ASIC,与标准SRAM相比,它们需要更多的电路面积和功率。另一方面,基于可编程逻辑(例如现场可编程门阵列(FPGA))的设计只能使用FPGA提供的通常不包含TCAM的模块。在后一种情况下,可以使用FPGA逻辑资源来仿真TCAM,但成本较高。为了降低实现TCAM的成本,已经提出了许多算法解决方案,这些解决方案被称为算法TCAM或A-TCAM。这些方案大多数针对软件或ASIC实现。在本文中,我们提出了针对FPGA实现的A-TCAM解决方案-多个哈希匹配单元(MHMU)。所提出的方案利用FPGA的大规模并行性来实现许多基于散列的匹配单元,这些单元使用FPGA的嵌入式Block RAM存储器。拟议的MHMU方案已映射到Xilinx系列7 FPGA,以检查其在资源使用和可扩展性方面的效率。为了验证MHMU的有效性,已经使用Classbench生成的规则集测试了一个简单的配置。结果表明,MHMU能够一致地容纳带有大键的成千上万条规则的集合。

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