Design and Analysis of Cost-Efficient Ultra-High-Order Matched Filter Architecture Using 4-Phase Calculating Paths for Underwater Applications

摘要

In this paper, we propose a cost-efficient VLSI hardware design of matched filter architecture for underwater applications, especially for ultra-high-order demands. By using proposed 4-phase calculating paths, it aims to reuse the main hardware components and extremely saves the hardware cost without any system performance loss. In a design implementation via TSMC 40-nm CMOS technology, an 80-tap matched filter hardware only requires a synthesis design area of 0.061 mm