High Throughput Hardware Implementation for Deep Learning AI Accelerator

摘要

In this paper, a high-throughput hardware accelerator for deep learning neural networks is proposed. Since deep learning operations require high data access from DRAM, we design a high data reuse architecture to reduce the data access directly from external DRAM and provide a pipeline scheme to achieve high throughput requirements. The architecture proposed in this paper uses INT8 precision computing, 128-bit AXI bus protocol, and parallel processing with 16 sets of processing units, and achieved real-time operation at 125 MHz operating frequency and 8GOPS throughput.