Compact SPICE Models of the Standard Layout Fragments in LSI Interconnections

摘要

Authors propose a compact SPICE model of LSI interconnections providing high accuracy of simulation in a time domain with considerable reduction of simulation time. Both straight sections of interconnections, bends with angles 90° and 135° and also T-shaped branches of interconnections are considered. The interconnection model in the form of a multilink RC circuit is taken as a basis. For use in a time domain, the two-section model, both long straight sections of interconnections, and bends is offered. The multi-section RC circuits and the equivalent two-section model were simulated. Using the two-section model, CPU time is reduced by 20%. At the same time the error of the two-section model is 2% in a time domain.