An Automatic Testbench Generator for Test Patterns Validation

摘要

The growing size and complexity of digital ICs, along with the requirement for better test quality (high test coverage of diversified fault type models) had resulted in an explosion of test data volume and complicated test protocols. What used to be a recommended optional step in the past, is becoming a mandatory and even a crucial step for the overall test process efficiency. Test patterns validation allows for early detection of issues introduced by successive and cumulative modeling and processing steps (from DFT insertion to ATPG generation). The earlier issues are detected, the better in term of debug and fix time point of view, thus in term of test cost. The expensive ATE time should be made profitable by reserving it to only screening real defect issues on the test chip. In this paper, we address the problematic of efficient test pattern validation. Almost no literature exists concerning this area, and giving its current and future growing criticality, we start addressing this domain with a set of innovative ideas that have been implemented in an industrial tool. Unlike some existing solutions that use a PLI (Programming Language Interface) based approach, the proposed tool is a standalone tool, that translates a cycle based test pattern file to an equivalent event based HDL (Hardware Description Language) testbench for sake of validation under logic simulator. Industrial experiments demonstrated that this novel tool is surpassing our previous PLI based tool in terms of performance (> 2X runtime improvement and > 3X memory consumption saving), while achieving better results in terms of robustness and validation confidence. As a matter of fact, it has gained a major success where it is now adopted by our customers worldwide.