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Assurance of Fault-Tolerance in Bit-Stream Computing Converters

机译:比特流计算转换器中的容错保证

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摘要

The article is devoted to the approach to the construction of original bit-stream devices, characterized by the high fault-tolerance. This property is achieved due to the original structure of the devices, fault-tolerant forms of information representation and the use of an elemental base with the high degree of technological reliability. A bit-stream multiplier-divider unit is considered as an example; its RTL description is presented. The results of the multiplier-divider unit simulation are shown; the process of the result recovery after the noise influence is presented.
机译:本文致力于以高容错为特征的原始比特流设备的构建方法。由于设备的原始结构,信息表示形式的容错形式以及使用具有高度技术可靠性的基本元件而实现了此特性。以比特流乘法除法器为例。介绍其RTL描述。显示了乘数除法器单元仿真的结果;介绍了噪声影响后结果恢复的过程。

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