Tutorial: Macro-modeling for solving SOC physical design automation problems

摘要

Large-scale combinatorial optimization problems arise in many areas. One of them is SoC Design Automation. Such problems as partitioning, packaging, placement, routing and compaction are very complex. From mathematical point of view, these problems belong to intractable combinatorial. Optimization is especially important for VLSI, SOC and NoC design. The complication of the electronic circuit requires a further search for the new robust approaches to solve such problems with high quality. New basic approaches and algorithms were developed for the hierarchical circuit clustering, partitioning, packaging, and placement by hierarchically built clusters, as well as for flexible (topological-geometric) routing.