Analog generators, especially those used for automatic layout creation, are powerful tools to support the still largely manual analog design flow. The effort for generator development, however, is often found to be a bottleneck. Further, verification of generators is usually based on many cycles of generation, each requiring subsequent verification. This is often expensive in terms of computation effort. Up-to-date generators only allow to detect failures using post-layout checks such as DRC and LVS because they describe the designer's intent implicitly as a sequence of (layout manipulation) commands which cannot be verified directly. Also, sequential code often prevents the description of interdependent layout structures or forces the programmer to include extra code, which can again cause errors. In order to overcome these issues, we introduce a new approach to implement layout generators. In a first step, the layout is described as an abstract template. A second automatic step checks this template for structural errors and schedules the required procedural commands. As the result, layout generators are more compact, easy-to-read, and errors can be detected by formal checks of the template description. The new approach was applied to two technology nodes, 180 nm and 22 nm.
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