The Role of Dynamic Reconfiguration for Implementing Artificial Neural Networks Models in Programmable Hardware

摘要

In this paper we address the problems posed when Artificial Neural Networks models are implemented in programmable digital hardware. Within this context, we shall especially emphasise the realisation of the arithmetic operators required by these models, since it constitutes the main constraint (due to the required amount of resources) found when they are to be translated into physical hardware. The dynamic reconfiguration properties (i.e., the possibility to change the functionality of the system in real time) of a new family of programmable devices called FIPSOC (Fleld Programmable System On a Chip) offer an efficient alternative (both in terms of area and speed) for implementing hardware accelerators. After presenting the data flow associated with a serial arithmetic unit, we shall show how its dynamic implementation in the FIPSOC device is able to outperform systems realised in conventional programmable devices.