High Performance Low Cost Multicore NoC Architectures for Embedded Systems

摘要

With multilayer multistage interconnection networks, a very efficient network-on-chip topology for multicast traffic in multicore processors is introduced. This paper describes how MLMINs are established and what parameters determine such an architecture. Performance and cost of MLMINs are calculated and compared to other proposed NoC topologies. It turned out that the MLMIN architecture shows a better performance or at least similar performance in terms of throughput if network costs are equal. The delay times of MLMINs heavily undercut those of replicated MINs. Thus, multicore architectures using MLMINs are obvious candidates for the implementation of compute-intensive embedded systems.