IMPACT OF WAFER BACKSIDE CU CONTAMINATION TO 0.18 μm NODE DEVICES

摘要

The impact of wafer backside Cu contamination to 0.18 μm node devices under thermal anneal was studied. Prior to Cu contamination, SiN film on wafer backside was removed to ploy silicon or silicon substrate. The Cu contamination level ranged from below 1 x 10~(10) to above 1 x 10~(16) atoms /cm~2, and the wafers were annealed at 350 to 450℃ for 7 hours. Device electrical parameters were tested prior and after contamination. No threshold voltage shift and junction current leakage increase was observed from Cu contamination. Even with >1 x 10~(16) atoms/cm~2 Cu contamination on bare Si backside and anneal at 450℃, no gate oxide degradation to 0.18 μm node devices was detected either.