Design and Realization of DPLL used in SDH equipment Clock

摘要

A novel digital phase locked loop(DPLL) used in SDH equipment Clock is proposed in this paper. The output frequency of this DPLL is 155.520MHz which is the most used timing frequency in SDH transmission system. The time resolution of phase detector in traditional DPLL is low, and then it is not fit for the DPLL in 155.520Mbit/s system. In our new DPLL, the phase detector is implemented with a time-to-digital converter whose time resolution is 200ps. With the improvement of phase detector, the DPLL shows excellent performance. The DPLL meets the requirement given in ITU-T Recommendation G.813, and has been used in our SDH transmission system.