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Study of warpage characteristics of molded stacked-die MCP using Shadow Moiré and Micro Moiré techniques

机译:利用ShadowMoiré和MicroMoiré技术研究模压叠层MCP的翘曲特性

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As the mobile and consumer devices continue to demand for more functionality and less power within a smaller dimension, integration of IC packages becomes essential for the successful introduction of electronic devices in the market. Stacked-die packages are finding increased usages in SiP (system-in-package) and PoP (package-on-package), while various new packages based on CoC (chip-on-chip) and TSV (through-silicon-via) technologies are being developed. To ensure the reliability of assembled parts, the dimensional stability of stacked-die packages has to been properly controlled. This is to ensure a predictable performance of interconnections can be achieved after SMT/PoP assembly and at various operating conditions. Especially, warpage characteristics caused by thermo-mechanical stresses need to be considered in product design. In this study, a systematic study of single-die, four-die and eight-die land-grid-array (LGA) package warpage characteristics was carried out using both Shadow Moire and Micro Moire techniques. Shadow Moire was used to study the package warpage in a temperature range from room temperature to 260°C to simulate the solder ball reflow conditions; while a Micro Moire instrument, with a resolution of 417 nm without phase shifting, was used to understand localized stress distribution within the package between room temperature and 104°C. Effects of die sizes, die thicknesses, number of die stacked, type of molding compounds and mold cavity heights can thus be correlated. When using single die packages as a control, Shadow Moire measurement results showed molding compound types have a greater impact on package warpage than die thicknesses and mold cavity heights. In an eight-die MCP package, larger die size exhibited higher warpage during thermal cycling, whereas under same conditions choice of molding compound is insignificance to achieve improved performance. It was also found when die sizes and mold cavity heights were kept the-- same, four-die packages with approximately 3 times the die thickness exhibited slightly less warpage than that of eight-die packages. However, of the two, eight-die package exhibited dimensional changes within a narrower temperature range under reflow conditions. Micro Moire measurement results clearly showed the stresses were concentrated at the die edges between adjacent stacked dice. These results are useful for employing new designs lead to better product reliability.
机译:随着移动设备和消费设备在更小的尺寸内继续要求更多的功能和更少的功率,IC封装的集成对于成功将电子设备引入市场至关重要。堆叠管芯封装在SiP(系统级封装)和PoP(叠层封装)中的使用正在增加,而各种基于CoC(片上芯片)和TSV(直通硅通孔)的新封装技术正在开发中。为了确保组装零件的可靠性,必须适当控制堆叠式芯片封装的尺寸稳定性。这是为了确保在SMT / PoP组装后以及各种操作条件下都能实现可预测的互连性能。特别地,在产品设计中需要考虑由热机械应力引起的翘曲特性。在这项研究中,系统地研究了单模,四模和八模陆地栅格阵列(LGA)封装翘曲特性,同时使用了阴影莫阿和微莫尔技术。 Shadow Moire用于研究从室温到260°C的温度范围内的封装翘曲,以模拟锡球回流条件;而使用Micro Moire仪器(分辨率为417 nm,没有相移)来了解室温和104°C之间封装内的局部应力分布。模具尺寸,模具厚度,模具堆叠数量,模塑料类型和模腔高度的影响因此可以相互关联。当使用单模包装作为对照时,Shadow Moire测量结果表明,模塑料类型对包装翘曲的影响大于模具厚度和模腔高度。在八芯片MCP封装中,较大的芯片尺寸在热循环过程中会表现出较高的翘曲度,而在相同条件下,选择模塑料对于提高性能的意义不大。还发现,当保持模具尺寸和模腔高度时,相同的四模具封装的模具厚度大约是模具厚度的3倍,其翘曲比八模具封装的翘曲稍微小一些。然而,在回流条件下,两个八个芯片的封装在较窄的温​​度范围内显示出尺寸变化。 Micro Moire测量结果清楚地表明,应力集中在相邻堆叠晶粒之间的模具边缘。这些结果对于采用新设计以提高产品可靠性很有用。

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