Advances in WLCSP Technologies to Enable Cost-Reduction

摘要

Over the past few years, Wafer Level Chip Size Packages (WLCSPs) have gained widespreadrnadoption, due to their ability to deliver higher performance at lower or equivalent costs when compared torncompeting packages. WLCSPs have been an excellent fit for the handheld/portable industry, where thernstrong push for cost-reduction and miniaturization, coupled with relatively relaxed reliabilityrnrequirements, have motivated true chip-sized packages requiring no underfill or overmold. Reliabilityrnperformance initially limited the application of WLCSPs to small die sizes (<2.5mm), low pin countsrn(<25) and mature silicon technology nodes. Also, to date, a majority of WLCSPs have been built at arn0.5mm bump pitch, although there is increasing growth in the use of WLCSPs at 0.4mm pitch. Thesernfactors have allowed WLCSP packaging to flourish in the mixed signal and analog market space. Withrnthe maturity in this market segment, the WLCSP is beginning to transition from an advanced package to arncommodity package and is subject to the price-pressure that accompanies this transition.rnMore recently, the semiconductor industry has seen advances in WLCSP technology which have enabledrnthe qualification envelope to be expanded to products with pin counts > 120. These advances havernfacilitated the use of WLCSPs for other component types such as RF, high speed, broadband and memory,rnmany of which require advanced silicon technology nodes as well. Consequently, WLCSP is expandingrnto markets and applications previously supported by QFN and flip chip CSP. This expansion putsrnadditional price and cycle time pressure on WLCSP manufacturing. The cycle time pressure is furtherrnenhanced by the changing business models and supply chain strategies adopted by companies in the newrneconomic environment. To meet these growing market demands, WLCSP providers are faced with thernchallenges of providing faster cycle times and higher capacity without significant increases in capitalrnexpenditure.rnThe above factors have driven the need for new WLCSP technologies that utilize fewer process stepsrncompared to common WLCSP product offerings, while maintaining the robustness necessary for meetingrnquality and reliability requirements. Amkor is developing multiple WLCSP technology platforms to caterrnto the cost and performance requirements of the diverse application space.rnThis paper will provide examples that significantly reduce overall package cost by removingrnphotolithography layers. Each photomask layer removed saves in material costs, capital depreciationrncosts, overhead, and process cycle time. Materials, package size, and internal qualification vehicles arerncarefully chosen as part of Amkor’s product introduction for the proposed process flows. This paper willrnexamine material options, i.e., polymers and solder alloys, for these new structures and will also examinernthe effects of die sizes and I/O counts on product reliability. Detailed analyses of the failure modesrnproduced during reliability testing will be coupled with mechanical simulations to enhance understandingrnof the failure mechanisms and to further strategies for improving product reliability.