Thermal Stress Analysis for Geometry Dependence in 3-D Packaging with Through-Silicon-Via using Finite Element Method

摘要

Through-silicon-via (TSV) technology becomes wildlyrnapplied for 3-D integration. Thermal stress can affect thernreliability because Cu has about 6 times higher Coefficient ofrnThermal Expansion (CTE) than surrounding materials such asrnSi. Thermal stress is predicted to increase in stacked wafersrnpackaging. However, there are few researches about reliabilityrnissues related to thermal stress in those systems mentionedrnabove. In this paper, thermal stress was analyzed using finiternelement method (FEM) with variation of TSV and bondingrndiameter, pitch and wafer thickness. The designed model has arnstructure of two wafers on the PCB, using Cu-Sn-Cu to bondrneach layer. The thermal load was from 250°C to 50°C. Thernmaximum von Mises stresses occurred at the edge of toprninterface between Cu TSV and Si, the Si to Si bonding and thernPCB to Si bonding. As TSV diameter increased, the von Misesrnstress at the edge of TSV increased. As bonding diameterrnincreased, the von Mises stress at Si to Si bonding increased.rnAs pitch increased, the von Mises stress at Si to Si bondingrnand PCB to Si bonding increased. The wafer thickness did notrnaffect the von Mises stress. In conclusion, smaller Cu TSVrndiameter and pitch showed higher reliability, since the chancernof plastic deformation and crack decreased with reducing them.