Optimal Design of Multiplying and Dividing Circuit for Reed-Solomon ECC Codec Processor

摘要

This paper describes how to design a Galois field Multiplying and dividing circuit using sub field theory[4]. The circuit is much faster and more economical than the classical circuit. Multiplier circuit is a part of Divider and there is no inverse ROM for the dividing operation. We compared the new design with the classical design in both respects, speed and cost so found the new design is much better than the classical design.