Interconnect Optimization by Semidefinite Programming

摘要

A method to optimize delay and power dissipation in on-chip interconnect is reported. Propagation delay can be represented by the dominant time constant of the corresponding RC circuit or as a p-q% delay. The optimization problem is formulated as a sequence of semi-definite programming problems. The method is applied to interconnect with inclusion of the fringing capacitance and capacitive coupling between wires. Shapes of single wires and models of real-life bus designs are optimized. It is shown that the optimal wire shape depends on the chosen delay metric and that it can be described accurately with a linear model. The differences between wire sizing and wire tapering are discussed. The importance of capacitive coupling in the optimization of multi-wire buses is demonstrated. Future extensions of the approach are discussed.