In this paper, a novel simultaneous multi-channel data acquisition system is proposed. Analog signals with different bandwidths are applied to an analog multiplexer with a single analog to digital converter. A novel scalable adaptive Heterogeneous Maximum Service (HMS) scheduler is designed to detect different bandwidths in order to determine the proper sampling rate for each input signal. The analog multiplexer is adaptively controlled to switch between the analog signals of variable bandwidths. The target technology of implementing the proposed design is the Field Programmable Gate Array (FPGA). The Analog-to-Digital Converter interface and the adaptive scheduler are implemented in the FPGA using hardware description language. The synthesized prototype used only 11% of the total logic elements (of Altera Cyclone II, EP2C35F672C-6N FPGA) and 15% of its total memory bits. The worst-case prorogation delay observed for the system is 12.04 ns, which is less than the 50 MHz clock period of 20ns. The Cyclone-II FPGA consumes power as low as 12 mW. The proposed acquisition root mean square of error is 2×10-15. The proposed system can be used in various applications that require heterogeneous multi-channel data acquisition system such as biomedical devices.
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