Analysis and Reduction of Noise in Fractional PLL

摘要

The aim of this paper is analysis and presenting a technique to reduce phase noise in fractional frequency synthesizer for pure signal synthesis. To reduce phase noise of synthesizer, first, we present a mathematical and accurate model of noise in Phase Locked Loop(PLL) based fractional frequency synthesizer with take into account noise of its component. Then we predict output phase noise in term of its parameters. Finally, we describe as effective technique for noise in fractional frequency synthesizer by CppSim simulator. The Behavioral Simulation results show the performance of the fractional frequency synthesizer.