In an attempt to circumvent the weaknesses and limitations of the conventional control-flow and data-flow models of computation, a new model of computation, called associative dataflow, is proposed, which eliminates the token-matching operation degrading the performance of the traditional dataflow systems. The architecture of an associative dataflow processor, reflecting the hardware realization of the proposed model of computation, has been presented in this paper. All components of the processor have been designed and simulated using Mentor Graphics design tools, and the peak performance as well as the benchmark performance of the associative dataflow processor have been evaluated and compared with the existing dataflow systems. Finally, informantion about the dimensions of the integrated circuits layouts for various components within the processor has been tabulated.
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