Dataflow computation with intelligent memories emulated on field-programmable gate arrays(FPGAs)

摘要

This paper presents a new design that implements the data-driven(i.e. dataflow)computation paradigm with intelligent memories. Also, a relevant prototype that employs FPGAs is presented for the support of intelligent memory structures. Instead of giving the CPU the privileged right to decide what instructions to fetch in each cycle(as is the case for control-flow CPUs), instructions in dataflow computers enter the execution unit on their own when they are ready to execute. This way, the application-knowledgeable algorithm, rather than the application- ignorant CPU, is in control.