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Parallel Heterogeneous Architectures for Efficient OMP Compressive Sensing Reconstruction

机译:高效的OMP压缩传感重建的并行异构架构

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Compressive Sensing (CS) is a novel scheme, in which a signal that is sparse in a known transform domain can be reconstructed using fewer samples. The signal reconstruction techniques are computationally intensive and have sluggish performance, which make them impractical for real-time processing applications . The paper presents novel architectures for Orthogonal Matching Pursuit algorithm, one of the popular CS reconstruction algorithms. We show the implementation results of proposed architectures on FPGA, ASIC and on a custom many-core platform. For FPGA and ASIC implementation, a novel thresholding method is used to reduce the processing time for the optimization problem by at least 25%. Whereas, for the custom many-core platform, efficient parallelization techniques are applied, to reconstruct signals with variant signal lengths of N and sparsity of m. The algorithm is divided into three kernels. Each kernel is parallelized to reduce execution time, whereas efficient reuse of the matrix operators allows us to reduce area. Matrix operations are efficiently paralellized by taking advantage of blocked algorithms. For demonstration purpose, all architectures reconstruct a 256-length signal with maximum sparsity of 8 using 64 measurements. Implementation on Xilinx Virtex-5 FPGA, requires 27.14 μs to reconstruct the signal using basic OMP. Whereas, with thresholding method it requires 18 μs. ASIC implementation reconstructs the signal in 13 μs. However, our custom many-core, operating at 1.18 GHz, takes 18.28 μs to complete. Our results show that compared to the previous published work of the same algorithm and matrix size, proposed architectures for FPGA and ASIC implementations perform 1.3× and 1.8× respectively faster. Also, the proposed many-core implementation performs 3000× faster than the CPU and 2000× faster than the GPU.
机译:压缩感测(CS)是一种新颖的方案,其中可以使用较少的样本来重建在已知变换域中稀疏的信号。信号重建技术计算量大且性能低下,这使其不适用于实时处理应用程序。本文介绍了正交匹配追踪算法(一种流行的CS重建算法)的新颖架构。我们展示了在FPGA,ASIC和定制的多核平台上提出的架构的实现结果。对于FPGA和ASIC实现,使用了一种新颖的阈值处理方法,可以将优化问题的处理时间至少减少25%。而对于定制的多核平台,应用有效的并行化技术来重建信号长度为N且稀疏度为m的信号。该算法分为三个内核。每个内核都经过并行处理以减少执行时间,而矩阵运算符的有效重用使我们能够减少面积。通过利用分块算法,可以有效地并行处理矩阵运算。出于演示目的,所有架构都使用64个测量值来重建最大长度为8的256长度信号。在Xilinx Virtex-5 FPGA上的实现需要27.14μs的时间才能使用基本OMP重建信号。而使用阈值方法则需要18μs。 ASIC实现在13μs内重建信号。但是,我们的定制多核工作频率为1.18 GHz,需要18.28μs的时间才能完成。我们的结果表明,与先前发布的具有相同算法和矩阵大小的工作相比,针对FPGA和ASIC实现提出的架构分别执行了1.3倍和1.8倍的速度。同样,提出的多核实现的执行速度比CPU快3000倍,比GPU快2000倍。

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