Compensating for SSIS sizing/classification error In a Defect Review SEM World

摘要

As the Integrated Circuit manufacturing market has begun a concerted effort toward the mass production of 45nm node material, the emergence of inaccurate defect sizing and subsequent mis-identification of surface and subsurface defects from Surface Scanning Inspection Systems (SSIS) has become a major impediment for accurate Scanning Electron Microscope (SEM) Automated Defect Redetection (ADR) and Automated Defect Classification (ADC).Due to the increased manufacturing cost of Silicon Wafers (Silicon on Insulator, Strained Silicon, Strained Silicon on Oxide, Silicon on Silicon Germanium) and the desire from IC manufacturing companies for a continually increasing level of Incoming Quality Assurance (IQA) wafer cleanliness, the cost of IC manufacturing has dramatically risen in recent years.The increased cost of manufacturing for both IC manufacturing and Silicon Wafer manufacturing is driving the requirement for a high throughput Defect Review SEM that is able to independently overcome the defect sizing and defect classification challenges from both the 45nm and 90nm nodes. The benefits of improved SEM ADR and ADC performance must not come at the expense of the SSIS throughput.This paper provides a study of the methods employed in multiple manufacturing lines to provide rapid feedback of yield impacting defects, allowing for improved root cause analysis and improved fab productivity.