DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems

摘要

To effectively manage power in Globally-Asynchronous Locally-Synchronous (GALS) systems with many interconnected nodes, each should be ideally provided with an individual Dynamic Voltage and Frequency Scaling (DVFS) mechanism. However, full-blown DVFS requires complex voltage regulators and PLL or DLL circuits. To reduce the difficulty of integrating many complex DVFS controllers, we propose a DVFS system that makes use of 1) voltage dithering between a few voltage levels, 2) a scheduler that selectively kills ticks of a high-frequency clock to create an “effective” clock frequency and 3) a local distributed clock-gating mechanism that periodically stalls the registers of a pipeline without incurring the penalties of global clock gating. We report results obtained on a CMOS 45 nm technology and show that the behavior is close to that of an ideal DVFS, even with only two voltage levels.