Adaptive Packet Switch with an Optical Core (Demonstrator)

摘要

A three-stage optoelectronic packet switch architecture is described consisting of a reconfigurable optical centre stage surrounded by two electronic buffering stages partitioned into sectors to ease memory contention. A Flexible Bandwidth Provision (FBP) algorithm, implemented on a soft-core processor, is used to change the configuration of the input sectors and optical centre stage to set up internal paths that will provide variable bandwidth to serve the traffic. The switch is modeled by a bipartite graph built from a service matrix, which is a function of the arriving traffic. The bipartite graph is decomposed by solving an edge-colouring problem and the resulting permutations are used to configure the switch. Simulation results show that this architecture exhibits a dramatic reduction of complexity and increased potential for scalability, at the price of only a modest spatial speed-up k, 1 < k < 2. The packet switch is implemented on separate programmable logic devices forming electronic "islands" interconnected by photonics technology. The demonstrator design has 8 inputs and 8 outputs with reconfigurable central stage crossbars. Each sector is a 4x4 sub-switch implemented on a single FPGA with shared buffer memory. Communication among entities is performed through a high speed 10 Mbps link.