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A Branch Target Instruction Prefetching Technique for Improved Performance

机译:分支目标指令预取技术可提高性能

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Modern processors are much faster than the main memory. Cache memories are introduced to reduce this speed gap. However, instruction cache misses can severely limit the performance of today''s superscalar processors. Prefetch algorithms attempt to reduce
机译:现代处理器比主存储器快得多。引入了高速缓存以减少这种速度差距。但是,指令高速缓存未命中会严重限制当今超标量处理器的性能。预取算法试图减少

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